1. Technical Field
The present invention relates in general to integrated circuitry and, in particular, to a boundary scan cell of an integrated circuit. Still more particularly, the present invention relates to a high-performance IEEE1149.1-compliant boundary scan cell of an integrated circuit.
2. Description of the Related Art
A significant expense incurred during the manufacture of circuit cards carrying one or more integrated circuit components is testing. Such testing generally entails stimulating the input/output (I/O) pins of a circuit card with a predetermined pattern of inputs and then observing the outputs generated by the components residing on the circuit card. Several factors contribute to the expense of circuit card testing. First, because many circuit card components do not employ a standard I/O interface, circuit card testing fixtures tend to be complex and must often be custom-designed to test particular circuit cards. Second, the input pattern utilized to stimulate a circuit card must often be generated manually in order to ensure that circuit card components are exercised over a sufficient range of functionality to ensure high quality. Third, while it may be less expensive for a circuit card or component manufacturer to out-source testing to an outside contractor, the use of non-standard component interfaces can require the component manufacturer to reveal proprietary information concerning the internal design of a component to the component tester, making many manufacturers reluctant to engage an outside contractor to perform testing.
In order to decrease the cost and increase the quality of component testing, the IEEE (Institute of Electrical and Electronic Engineers) adopted the IEEE1149.1-1990 Standard Test Access Port and Boundary Scan Architecture (hereinafter referred to as the IEEE1149.1 standard). The IEEE1149.1 standard specifies that a boundary scan cell be inserted between the functional logic of a component and each of its input receiver and output driver circuits. These boundary scan cells, whose behavior is prescribed in detail by the IEEE1149.1 standard, are typically implemented with at least a 2-to-1 multiplexer in the direct path between the component's functional logic and the driver or receiver. For example, referring now to FIG. 1, there is depicted a high level block diagram of a conventional circuit card 10 bearing two integrated circuit chips interconnected through IEEE1149.1-compliant interfaces. As shown, integrated circuit chips 12 and 14 each include an edge-sensitive D flip-flop 20 that operates in response to clock signal 22. D flip-flop 20 of integrated circuit chip 12 has a data input (D) connected to the functional logic of integrated circuit chip 12, and D flip-flop of integrated circuit chip 14 has a data output (Q) connected to the functional logic of integrated circuit chip 14. Between each of D flip-flops 20 and a respective one of output driver 30 and input receiver 32 is a 2-to-1 multiplexer 24, which has a first data input tied to an IEEE1149.1-compliant boundary scan cell 26 and a second data input and a select input supplied by the associated boundary scan cell 26. The output of each of multiplexers 24 also forms an input of the associated boundary scan cell 26.
While the implementation of conventional IEEE1149.1-compliant interfaces within components, such as integrated circuit chips 12 and 14, facilitates higher quality, low cost testing without the need for disclosure of the internal circuitry of the components under test, these benefits come at the expense of performance due to the signal path delay associated with two multiplexers 24 and the signal path loading associated with boundary scan cells 26. Because of the performance penalty associated with conventional IEEE1149.1-compliant boundary scan cells, manufacturers have resisted compliance with the IEEE1149.1 standard for at least eight years. The present invention includes a recognition that it would be desirable to provide an improved boundary scan cell that complies with the IEEE1149.1 standard and is not subject to the performance penalty associated with conventional implementations.